Hands-on senior FEA/multiphysics specialist with deep expertise in Ansys Mechanical, focused on thermo-mechanical analysis and reliability prediction of semiconductor packages, PCBs, interconnects, and electronic assemblies.
Added value:
Leveraging mechanical simulation to understand and predict failure in semiconductor packages, PCBs, interconnects, and electronic assemblies. Provide physical problem needs to be modeled, what assumptions are defensible, which simulation results actually matter, and how those results relate to real hardware failure.
Ansys Mechanical: hands-on, daily practitioner.
Including APDL and workbench
Thermo-mechanical FEA:
Thermal cycling, temperature gradients, CTE mismatch, warpage and resulting stresses
Electronics packaging:
Chip/package interactions, BGA, QFN, flip-chip and solder/interconnect structures
PCB mechanics:
PTHs, microvias, board-level deformation and fatigue
Nonlinear/failure analysis:
Fatigue, plasticity and damage mechanisms where relevant to electronics reliability
Simulation/test correlation:
Connecting FEA predictions to accelerated reliability testing and field behavior
Modeling strategy:
Consulting and training for selecting an appropriate level of model fidelity and combining detailed FEA with more efficient analytical approaches when appropriate
Predicting package warpage.
C4 bump fatigue due to temperature cycling
Copper pillar chip attach (ELK stress) white bump prediction
Underfill cure shrinkage stress simulation
Thermal conduction in GAAN GAS and SiC devices
Delamination and cracking stresses in stacked wideband semiconductor packages
Stacked die and mixed die (wirebond and flip chip) failure modes prediction
Gold pad fatigue on SiC die with Copper pillar
Automotive connector snap-fit simulation
Copper fatigue and delamination in PCB/substrate traces and vias
Pad cratering prediction using IPC 9704 test correlation
Interconnect stress simulation in AlN devices on organic substrates
Crimp simulation for wire connector assemblies
Hot tear simulation for solder reflow cooldown profile parameters.
Board level reliability: solder fatigue due to temperature cycling for BGA, QFN, Through hole, leaded and other SMT components.
Multi Chip Module MCM and System in Packag (SiP) thermal conduction and stress simulation
Mehcanical shock, Vibration and drop simulations of PCBs at component, PCB and box level
Rigid Flex PCB trace simulation for bend radius and induced stresses
Inter-metallic Compound cracking in Copper pillar design
Copper pillar on trace orientation and design for chip attache success
RDL and on-die crack stop structures simulation in GDS2
Silicon Die cracking due to overmold cure shrinkage
Excessive QFN warpage effect on temperature cycling solder fatigue
PCB connector fretting simulation
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