The first step in packaging silicon is chip attach. At the end of this process the silicon die is soldered to the substrate. The substrate is like a miniature circuit card that helps connect the very very small pads on the die to larger pads on the circuit card.
There are many types of substrates or lead frames but the attach process is mostly solder reflow. (The thermal compression non conductive polymer TCNCP method is not as common).
The die is soldered with the active layer facing the “top” and the backside of the die towards the “bottom”. The direction of “top” means that the active layers and exposed die pads are facing away from the substrate. The “bottom” or “backside” of the die is facing the substrate. The substrate has an exposed copper pad, usually one millimeter wider than the die on each side, with solder paste.
Reflow: Temperature goes up - The die sits on the solder paste and floats on the molten solder during the high temperature dwell of the reflow process.
Cooldown: Temperature goes down - As the temperature is decreased, the solder solidifies and effectively welds the die to the copper pad. During the cooldown process, the die , solder and substrate CTE mismatch cause stress. The temperature changes by as much as 200 degrees C, so even a small CTE difference causes a lot of deformation. Most of the stress goes to causing damage and deformation in the solder because the solder is the softest material.
The active layers are usually shielded from most of the damage because they are not in contact with the solder. The silicon die resists bending quite well and also acts to shield the active layers. It is possible to stack dies in a single package. Except for the top most die, all the rest of them will now have a die stacked on the active layers. However only the bottom die experiences the CTE mismatch between silicon and the substrate. The other stacked dies are all made of silicon and will have smaller CTE induced deformation and smaller stress.
The die is soldered with the active layer facing the “bottom” and the backside of the die towards the “top”. The direction of “bottom” means that the active layers and exposed die pads are facing the substrate. The “top” or “backside” of the die is facing away from the substrate. (This is the origin of the name “flip chip” because the chip is flipped. We are not very creative with the naming here). The substrate has many small exposed copper pads in a pattern matching the die pads with solder paste.
Post-fab processing: the UBM – While it might be possible to solder the Aluminum die pads directly to the solder on the substrate, that is difficult. Instead, packaging manufacturers will prepare the flip chip for the substrate by plating several layers of metal called the Under Bump Metallurgy UBM. The UBM is made of thin-film Aluminum Nickel, Copper, Titanium and any other alternative that the packaging engineers can think up. The last layer is usually copper plating.
Reflow: Temperature goes up – The individual solder die bumps melt together with the individual solder paste areas on the substrate copper pads. The die is floating on many drops of solder during the high temperature dwell of the reflow process. They can number in the thousands and look like a squished beach ball about 100 micrometers in diameter and 70 micrometers in height.
Cooldown: Temperature goes down - As the temperature is decreased, the solder solidifies at each individual solder connection. During the cooldown process, the die , solder and substrate CTE mismatch cause stress. Again, the temperature changes by as much as 200 degrees C, so even a small CTE difference causes a lot of deformation. The solder wants to deform and in a very slow cooldown, it would. At fast cooldown rates, the solder does not have time for shear deformation and instead applies a moment on the pads. The UBM is usually more sensitive to the applied moment because it is connected to the active layers of the die.
Flip chip active layers are directly facing the Solder and are more sensitive to brittle fracture during the reflow process. In an acoustic microscope, this damage looks like white circles where the active layers are broken and prompted the name “White Bumps” for this defect (We are not very creative with the naming here either). This is a “Distance to Neutral Point” DNP issue and we see white bumps at the corners of the die farthest away from the center of the die. This can happen anywhere in dies with severe depopulation or die pad patterns with large pitch changes.
Enter the Copper Pillar (CuP)
Copper pillars are used to make higher density and finer pitch connections possible. The C4 bump works well at 100-120 micrometers diameter. This also creates a 50-70 micrometer gap height between the substrate and the die. This gap height is needed to cause the capillary action of the underfill that is applied after the chip-attach process. The underfill is a viscous glass filled epoxy liquid that is carefully dispensed and later cured at high temperature. If the gap is too small or too big, the capillary action does not work and the underfill has voids and other defects.
Without the need for underfill, there is no reason why a solder bump can’t be 2 micrometer (Reliability is another issue, but theoretically possible). With underfill, a 30 micrometer bump will not work.
The copper pillar is like taking the last copper layer in the UBM and plating it to 30-40 micrometers instead of a thin film. A 15-20 micrometer solder “cap” is added on each pillar. This copper and solder combination can have a diameter that is 20-50 micrometer as compared to a regular 110 micrometer C4 bump. The copper pillar height can be changed to match the needed gap height while allowing higher density connections.
Copper pillars are stiff – the copper in the pillar is stiff and there is less solder in the total connection between the die and substrate. The solder needs even slower reflow cooldown rates to prevent the moment force on the copper pillar causing brittle fracture of the active layers on the die. More moment = more damage.
Flip chip packages are ready after the underfill process in contrast to wirebonded packages. For wirebonded dies, the die attach does not create the I/O connection. The gold or copper wirebonds to the top of the die need a protective epoxy overmold. A flip chip works fine with the die “backside” exposed (where a heat sink can be attached directly for thermal conduction), but the die does not need additional protection of an overmold. This is called a “bare die” flip chip (As usual, we are not very creative with the naming here)
The underfill cure process can also cause damage, but that is a different story.
Copyright Gil Sharon May 19, 2025 . All rights reserved.