Chip Packaging Basics

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The chip

The chip is a Silicon die. Silicon is a stiff, brittle ceramic material with a low CTE (3ppm/ºC). The terms “die” and “chip” are used interchangeably in the context of “chip packaging”.

The Silicon rectangle has layers with metal conductor and a ceramic dielectric printed on it. All of the circuitry is sometimes called the “Active layers”. The thickness of the Silicon die is between 800 to 60 microns. The active layers could be as small as 5 microns. The last or “top” layer has exposed Aluminum (Al- A L not A I) pads that are used to connect the integrated circuit (IC) to the rest of the electronic circuit.

Wirebonds

The die top has one or two rows of Aluminum pads along the perimeter. The die bottom is soldered to a large copper pad. This large pad provides electrical and thermal functions together with the mechanical connection. A wire bonding machine heats a gold (or copper, but mostly gold) wire tip and pushes the wire on the Al pad. The wire is then bonded to a pad on the PCB, making an electrical connection. The wires are very sensitive and need to be protected by an epoxy encapsulation.

Lead frame and Substrate

Many dies and wirebonds are so sensitive and require such delicate handling that they are sold as a package. The die is manufactured in the “Fab” and sent to a chip packaging facility. The chip packaging will make a miniature circuit card that has a solder pad for the die and capture pads for the wirebonds. This part package is epoxy encapsulated and sent to PCB assemblers who will then solder it to the PCB.

Some dies are packaged in a “lead frame” and others are on a “Substrate”. Lead frames are simpler and meant for creating leaded packages. The leads from the lead frame are initially flat and are later shaped either by the package manufacturer or the user. Substrates are more complex and are basically a small PCB.

Flip chip

Complex chips need more pads than can be connected with wirebonds along the perimeter. For complex circuits, the Aluminum pads are arranged in a grid like pattern on top of the die. The exposed Aluminum pads are plated with Copper (and other materials) and a Tin-Silver (SnAg) solder is stenciled and reflowed on the Copper. (The combination of Copper and other metal plating on top of the Aluminum pads is called the “Under-Bump-Metallurgy” or UBM for short). The final product has the Silicon die with the active layers, (the top layer has a passivation), a UBM and a solder sort-of-sphere called a “Bump”.

The substrate (a mini PCB) has copper pads in the same grid pattern as the die with the same solder paste stenciled but not reflowed. The die is then flipped so that the top of the die is facing the copper pads on the substrate. Each bump contacts a copper pad with solder paste and the reflow process collapses the solder bump and paste together in a controlled manner to form the Chip-Package solder joint. This is called a “Controlled Collapse Chip Connection” or C4 bump.

C4 bumps

The Controlled Collapse Chip Connection (C4) bumps are about 120 microns in diameter but can be as small as 30 microns and as large as 300 microns. A chip that is directly connected to a PCB without a substrate is sometimes called a “Chip Scale Package” (CSP) and usually has the larger bumps. The bumps usually need an underfill (epoxy adhesive that connects the die to the substrate). The C4 bumps are also susceptible to solder fatigue like any other solder joint. 

Copyright Gil Sharon May 1, 2025 . All rights reserved.